One knows switching devices such as single-stage packet switching nodes. Such nodes have a given, inherent implementation complexity. Namely, in an N-port packet switch, there is an N-to-N connection problem that leads to quadratic complexity. Although there are many different switch architectures (e.g., input-queued, output-queued, combined input- and output-queued, shared memory, etc.), this complexity manifests itself in all of these architectures in some way.
This complexity essentially stems from the non-blocking requirement, which requires that any one-to-one communication pattern (permutation) can be routed without conflicts. The complexity can only be reduced by relaxing this requirement, i.e., by allowing conflicts to occur even between communications from/to different ports. This leads to blocking switch architectures, which are usually based on a shared medium such as a bus or on a multi-stage arrangement. A disadvantage of such approaches is the limited aggregate throughput achievable due to physical limitations of e.g. a bus-based implementation.
Most existing single-stage switching node implementations satisfy the non-blocking requirement, i.e., they provide the capability to send at full capacity from any input port to any output port. In the specific case of crossbar-based architectures (which may be buffered or unbuffered), this implies that the switching node comprises N2 crosspoints. Moreover, in the case of buffered crossbar architectures, each crosspoint comprises a buffer that is sized to allow full link utilization over a full round-trip. In many cases, it can be realized that much of this buffering capacity will go largely unused, which represents a waste of precious resources.